1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, the present invention relates to a semiconductor memory device comprising a large-scale integrated circuit such as a dynamic random access memory (hereinafter referred to as a dynamic RAM).
2. Description of the Prior Art
FIG. 1 shows an arrangement of a conventional dynamic RAM and FIG. 2 shows an arrangement of a sense amplifier portion included in a conventional dynamic RAM.
First, referring to FIG. 1 a typical arrangement of a conventional dynamic RAM will be described. In FIG. 1, a memory cell array MCA comprises word lines WL, bit lines BL and a sense amplifier array SAA. Although a plurality of word lines WL and bit lines BL are provided in a memory cell array MCA according to the memory capacity, only one word line and one bit line are shown in FIG. 1.
Referring to FIG. 2, a sense amplifier in the end portion of the sense amplifier array SAA surrounded by a, b, c and d in FIG. 1 will be described in the following. One end of each of the aluminum leads SBL1, SBL1, . . . , SBL3 in the sense amplifier is connected to the associated bit line and the aluminum lead 1 short-circuits a cell plate of a memory cell not shown. The sense amplifier comprises insulated field effect transistors (hereinafter referred to as FET's), the FET's including gates G1, . . . G6 respectively. To one end of the aluminum lead 2, a sense amplifier activation signal is applied. The other ends of the aluminum leads SBL1, SBL1, . . . SBL3 are connected respectively to the drains of the FET's and the aluminum lead 2 is connected to the sources of the FET's. The regions surrounded by dotted lines in FIG. 2 represent activation regions for forming the sources and drains of the FET's.
In a conventional dynamic RAM, as shown in FIG. 2, the sense amplifiers are arrayed so that the distances d.sub.1, d.sub.2 and d.sub.3 between the aluminum leads of the adjacent sense amplifiers provided repeatedly with a certain cycle are equal respectively, while the distances d.sub.1a, d.sub.2a and d.sub.3a between the aluminum lead SBL1 of the outermost sense amplifier of the sense amplifier array SAA and the aluminum lead 1 provided further outside are different from the distances d.sub.1, d.sub.2 and d.sub.3. In the case of FIG. 2, the distances d.sub.1a, d.sub.2a and d.sub.3a are respectively smaller than d.sub.1, d.sub.2 and d.sub.3 .
FIG. 3 shows a state in which memory cells and sense amplifiers are connected. In FIG. 3, the bit line BL1 is connected with the drain of a FET QC1 forming a memory cell and the drain of a FET QD1 forming a dummy cell and further connected with the source of a FET QS1 forming a sense amplifier via the aluminum lead SBL1. The bit line BL1 is connected with the drain of a FET QC2 forming a memory cell and the drain of a FET QD2 forming a dummy cell and further connected with the source of a FET QS2 via the aluminum lead SBL1. To the respective drains of the FET's QS1 and QS2, an activation signal S is supplied. The gate of the FET QS1 is connected to the aluminum lead SBL1 and the gate of the FET QS2 is connected to the aluminum lead SBL1.
The word line WL1 is connected with the gate of the FET QC1 and the source thereof is connected with a capacitor CC1 so that a memory cell is formed by the capacitor CC1 and the FET QC1. In the same manner, the word line WL2 is connected with the gate of the FET QC2 and the source of the FET QC2 is connected with a capacitor CC2 so that a memory cell is formed by the capacitor CC2 and the FET QC2. The dummy word line DWL1 is connected with the gate of the FET QD1 and the source thereof is connected with a capacitor CD1 so that a dummy cell is formed by the capacitor CD1 and the FET QD1. In the same manner, the dummy word line DWL2 is connected with the gate of the FET QD2 and the source thereof is connected with a capacitor CD2 so that a dummy cell is formed by the capacitor CD2 and the FET QD2.
To a point of connection between the source of the FET QD1 and the capacitor CD1, the drain of a FET QR1 for discharging the dummy cell is connected. To a point of connection between the FET QD2 and the capacitor CD2, the drain of a FET QR2 for discharging the dummy cell is connected. To the respective gates of the FET's QR1 and QR2, a dummy cell reset signal RST is supplied.
The aluminum leads SBL1 and SBL1 may be connected electrically with floating capacities CS10 and CS20 for grounding potential and an interline capacity CS12 between the aluminum leads SBL1 and SBL1. Furthermore, the aluminum lead SBL1 may be connected with an interline capacity CS11 for the outer aluminum lead 1 and the aluminum lead SBL1 may be connected with an interline capacity CS23 for the adjacent aluminum lead SBL2.
The aluminum leads in the sense amplifiers are disposed so that each capacity associated therewith is almost equal to the sum of a floating capacity and an interline capacity. However, as shown in FIG. 2, the distance between the outermost aluminum lead SBL1 of the sense amplifier array SAA and the aluminum lead 1 existing further outside is smaller than the distance between other aluminum leads and accordingly, the capacity associated with the aluminum lead SBL1 is larger than the capacity associated with other aluminum leads.
Therefore, in order to dissolve the inequality of the capacities associated with the bit lines, a method may be considered in which the distance between an aluminum lead extending from the aluminum lead 1 to be disposed outside the bit line BL1 and the bit line BL1 is made equal to the distance between the bit line BL1 and the bit line BL2. However, even in this method, the capacity connected to the bit line BL1 and the capacity connected to the bit line BL1 would be different in the end because the capacity associated with the aluminum lead SBL1 and the capacity associated with the aluminum lead SBL1 are different as described above and in the example shown in FIG. 2, the capacity associated with the bit line BL1 (hereinafter referred to as CBL1) is larger than the capacity associated with the bit line BL1 (hereinafter referred to as CBL1).
FIGS. 4A and 4B are waveform diagrams showing a part of operation of a conventional dynamic RAM. Referring to FIGS. 4A and 4B, the operation of a dynamic RAM comprising bit lines, aluminum leads connected to the bit lines and an outer aluminum lead as described above will be described in the following, with regard to a case of reading the content stored in the capacitor CC1 of the memory cell shown in FIG. 3.
Let us first assume that the content stored in the capacitor CC1 is "1". First, the dummy cell reset signal RST rises to "H" and the FET's QR1 and QR2 are conducted so that the capacitors CD1 and CD2 are discharged. The bit lines BL1 and BL1 are precharged at the level "H" by precharge means not shown.
Then, after the dummy cell reset signal RST falls to the level "L", the word line WL1 and the dummy word line DWL2 are brought to the level "H" at the time t.sub.0. In consequence, the FET's QC1 and QD2 are turned on so that the bit line BL1 and the aluminum lead SBL1 are connected with the capacitor CC1 and the bit line BL1 and the aluminum lead SBL1 are connected with the capacitor CD2. As a result, the electric charge stored in the floating capacity CS10, the interline capacities CS11 and CS12 associated with the aluminum lead SBL1 and the electric charge stored in the capacitor CC1 are averaged. At the same time, the electric charge stored in the floating capacity CS20, the interline capacities CS23 and CS12 associated with the aluminum lead SBL1 and the electric charge stored in the capacitor CD2 are averaged.
At this time, the capacities associated with the bit lines BL1 and BL1 excluding the portions of the aluminum leads SBL1 and SBL1 are made almost equal and therefore, these capacities will not be particularly considered in this specification.
Generally, the capacity of the capacitor CC1 of the memory cell is made larger than that of the capacitor CD2 of the dummy cell and since the content stored in the capacitor CC1 of the memory cell is "1" and the capacitor CD2 of the dummy cell is discharged to be in a state corresponding to "0", the potential of the bit line BL1 is higher than the potential of the bit line BL1. At this time, the total capacity CBL1 associated with the bit line BL1 is larger than the total capacity CBL1 associated with the bit line BL1 as described above and as a result, the potential of the bit line BL1 precharged at the level "H" is hardly changed.
When the sense amplifier activation signal S falls to "L" to activate the sense amplifier, the FET QS2 is conducted and the FET QS1 is brought into a non conductive state since the gate potential of the bit line BL1, namely, the FET QS2 is higher than the gate potential of the bit line BL1, namely, the FET QS1, and as shown in FIG. 4A, the potential of the bit line BL1 is further lowered. As a result, the content "1" stored in the capacitor CC1 of the memory cell is correctly read out in the bit line BL1.
Now, the reading operation in the case of the content stored in the capacitor CC1 of the memory cell being "0" will be described. In this case, in the same manner as described above, the capacitors CD1 and CD2 of the dummy cell are discharged, the bit lines BL1 and BL1 are precharged and the word line WL1 and dummy word line DWL2 respectively rise to "H".
When the bit line BL1 and the aluminum lead SBL1 are connected with the capacitor CC1 and the bit line BL1 and the aluminum lead SBL1 are connected with the capacitor CD2, the potential of the bit line BL1 and the potential of the bit line BL1 are both lowered since the content stored in the capacitor CC1 is "0" and the capacitor CD2 is discharged to be also in a state corresponding to "0". At this time, the capacity CBL1 associated with the bit line BL1 and the capacity CBL1 associated with the bit line BL1 are in a relation of CBL1&gt;CBL1 as described above although the capacity of the capacitor CC1 is larger than the capacity of the capacitor CD2. If there is a large difference between the capacities CBL1 and CBL1, the potential of the bit line BL1 becomes higher than the potential of the bit line BL1 as shown in FIG. 4B. Accordingly, the FET QS2 is conducted and the FET QS1 is turned off and in consequence, the potential of the bit line BL1 does not correspond to the dotted line shown in FIG. 4B and on the contrary, the potential of the bit line BL1 is further lowered, which causes "1" to be read out in the bit line BL1. Thus, an error in reading occurs.
Since a conventional dynamic RAM is thus constructed, a difference in the capacities associated with the bit lines cannot be avoided to case an error in reading because the spacing between the aluminum lead SBL1 of the outermost sense amplifier in the sense amplifier array SAA and the aluminum lead 3 provided further outside is different from the spacing between the adjacent aluminum leads in the sense amplifier array SAA even if the bit lines the aluminum leads in the sense amplifier array SAA are arranged symmetrically.
Particularly in case where the distance between the aluminum lead of the outermost sense amplifier in the sense amplifier array SAA and the aluminum lead provided further outside is smaller than the distance between the respective adjacent aluminum leads in the sense amplifier array SAA, an error in reading is liable to occur when "0" is stored in the capacitor of the memory cell connected to the outermost bit line in the memory cell array. On the contrary, in case where the former distance is larger than the latter distance, an error in reading is liable to occur when "1" is stored in the capacitor of the memory cell connected to the outermost bit line in the memory cell array. Furthermore, if the degree of integration of semiconductor memories is increased and the spacing between the aluminum leads becomes narrow, the ratio of each interline capacity to the total capacity associated with the aluminum leads is increased, but if inequality exists in the interline capacities, reading operation of the dynamic RAM cannot be correctly performed.